1. Field of the Invention
The present invention relates to a chip size package and method of fabricating the same, more particularly to a chip size package having a plurality of solder balls arranged in array and method of fabricating the same.
2. Description of the Related Art
There are various types of semiconductor packages, such as, a small outline J-lead type(hereinafter "SOJ") for general use, a zigzag inline package type(hereinafter "ZIP") for particular occasion and a thin small outline package type (hereinafter "TSOP") for memory card which has been standardized.
Hereinafter, a method for manufacturing the above semiconductor package will be described.
In a sawing step, a wafer is cut along a scribe line thereby separating the wafer into individual semiconductor chips, and then a die attaching step is followed so that a lead frame is attached to each semiconductor chip.
Next, the semiconductor chip is cured at a given temperature and for a given amount of time. A wire bonding step is performed so as to electrically connect a bonding pad of the semiconductor chip and an inner lead of the lead frame by means of a metal wire.
After the wire bonding step, the semiconductor chip is molded with an epoxy compound (i.e. a molding step). By doing so, the semiconductor chip is protected from thermal or mechanical impacts originated from outer circumstances.
Afterward, an outer lead of the lead frame is plated (i.e. a plating step), and a dam bar supporting the outer lead is cut (i.e. a trimming step) and successively the outer lead is formed in a selected shape capable of easy mounting to a substrate (i.e. a forming step).
Most recently, a chip size package having approximately the same size of semiconductor chip has been developed instead of the above package manufactured according to foregoing procedure. The chip size package uses a Tape Automated Bonding (hereinafter "TAB") tape instead of the lead frame which is typically used in common package, and a plurality of solder balls arranged in array for mounting to a substrate.
In a conventional chip size package as shown in FIG. 1, a bump 2 is formed on a bonding pad of a semiconductor chip 1. A TAB tape 3 in which a metal pattern made of copper is formed, is attached to the bump 2 by thermal pressure and is electrically connected thereto. A resultant structure is completely molded with an epoxy compound 4, and then a solder ball is mounted on a ball land disposed on a lower portion of the TAB tape 3.
The conventional chip size package as constituted above, however, is required to improve its thickness-oriented drawback since the thickness of the TAB tape 3 including the epoxy compound 4 increases total thickness of the package while the trend in the package industry is to minimize its size.
There is a crack in the bump 2 or in the TAB tape 3, the crack is caused by a mechanical impact raised when the bump 2 and the TAB tape 3 are thermally pressed.
There is also generated a metal compound at a contact surface between the ball land and solder balls 5.
Especially, the TAB tape 3, itself includes remaining ions or moisture and there might be a malfunction in a package operation frequently. Furthermore, a short owing to a damage in an insulating film which insulates the metal pattern in the TAB tape 3, is occurred. Also, the TAB tape 3 is expected to redesign according to the changes in location and pitch of pads and solder balls.